Ion implanters are widely used in IC manufacture. Different styles implanters are used according to the different circumstances. When making transistors, shallow junctions need to be done with low energy but high dose. In 1978 a true high current ion implanter (current: 10 mA, energy: 80 keV) was firstly developed. After several decades study, the current of implanters reaches 40 mA, wafer size is increased from 50 mm to 300 mm.
The depth of source-drain junction decreases as the shrink of semiconductor devices sizes (beyond the 20 nm technology node), thus ultra-low energy implantation is needed to achieve a shallow junction. To achieve a low energy beam, usually the beam is extracted under a high energy (more than 1 keV) and then decelerated to a target energy (e.g. 700 eV) because of the space-charge effect. Yet before or during the deceleration, energy contamination is caused by neutral particles which are created by the charge exchange between ions and residual gas molecules. Apparently the energy contamination must be avoided since it will deteriorate the formation of the shallow junctions.
Besides, when 300 mm-sized wafers are used, the implantation could be implemented by wafers' 1D mechanically scanning and the usage of a uniform linear ion beam or a uniform ribbon-shaped beam. When wafer size increases to 450 mm, spot-shaped ion beam and 2D mechanical scanning are usually used. Under such circumstance, the uniformity of beam's intensity and angle needs to be ensured in order to achieve a high quality fabrication. Especially in 450 mm process, when a linear ion beam or a ribbon-shaped beam is used, the beam current intensity and angle must be uniform in a large dimension (>450 mm).
Therefore, ultra-low energy implantation is needed for forming a shallow junction as the integration is higher (e.g. 20 nm technology node). Meanwhile, the energy contamination must be avoided and the uniformity of beam current intensity and angle need to be ensured to achieve high quality when 450 mm wafers are to be processed. Thus, a new concept beam line to address the above requirements and to suit high-integrated, large-size wafers is needed.